In the past, (integrated) semiconductor devices fabricated in semiconductor substrates were generally isolated from each other in the same semiconductor substrate by some form of electrical isolation much as by PN junction isolation or by dielectric isolation.
Dielectric isolation as a means of electrically isolating semiconductor devices in one semiconductor substrate is generally preferred by semiconductor manufacturers because of the avoidance of junction breakdown that can occur when using PN junction isolation. Furthermore, because of lateral diffusion that occurs during various heat treatment operations, the use of PN junction isolated regions was not very desirable since increases in the lateral width of PN junction isolated regions resulted in reduction in device density for each semiconductor chip. Silicon real estate is very important in reducing costs and the loss of silicon real estate because of laterally expanding PN junction isolated regions was very undesirable.
Consequently, the preference of semiconductor manufacturers and especially integrated circuit manufacturers is to use dielectric isolation especially for sidewall isolation in manufacturing integrated circuit devices such as Complementary MOS (CMOS) devices. The most significant advantage of the use of sidewall dielectric isolation regions is the fact that they provide much better electrical isolation between devices such as for MOS or Complementary MOS devices.
However, in order to obtain maximum device (MOS or CMOS) density in one semiconductor chip, it is extremely important to find a way of how to restrict or limit the width of the sidewall dielectric isolation regions. Narrow width sidewall dielectric isolation regions will permit increased device (MOS or CMOS) densification and a resulting increase in the number of circuits that can be fabricated in each semiconductor chip. Therefore, increased device densification means a greater utilization of silicon real estate and a corresponding reduction in manufacturing costs because more MOS and/or CMOS devices can be fabricated in each semiconductor chip.
The above identified co-pending patent application provides a solution to producing narrow width sidewall dielectric isolation regions for the manufacture of integrated semiconductor devices and circuits, however, in carrying out the earlier dielectric sidewall isolation method, it was discovered that further changes in prior processes could provide significant improvements in both definition and yield.
Accordingly, a need existed for an improved method or process of forming narrow thermal silicon dioxide side isolation regions in a semiconductor substrate and MOS (or CMOS) semiconductor devices fabricated by this method or process.